1. Field of the Invention
The present invention relates to a semiconductor device and, particularly, to a semiconductor device having a vertical type bipolar transistor and a lateral type bipolar transistor.
2. Description of Related Art
The bipolar transistor has been used widely in almost all fields of semiconductor device covering high operation speed semiconductor integrated circuits to semiconductor integrated circuits of electronic devices for home use, in view of its high operation speed, its high driving performance and its superior analog characteristics.
There are two types of the bipolar transistor, that is, an NPN type bipolar transistor and a PNP type bipolar transistor, and it has been usual in an integrated circuit to use a vertical NPN transistor (referred to as "NPN transistor", hereinafter) having three impurity regions, an emitter, a base and a collector formed in a semiconductor substrate in a depth direction thereof in the order and a lateral PNP transistor (referred to as "L-PNP transistor", hereinafter) which can be formed without necessity of adding any steps to a fabrication steps of the NPN transistor.
FIGS. 4(a) to 4(d) are cross sections of a conventional bipolar integrated circuit having a NPN transistor and an L-PNP transistor, showing fabrication steps thereof in sequence.
First, as shown in FIG. 4(a), an N.sup.+ type buried layer 2 and a P.sup.+ type buried layer 3 are formed in a P.sup.- type silicon substrate 1 and then an N.sup.- type epitaxial layer 4 is grown thereon. Impurity density and thickness of the epitaxial layer depend upon a breakdown voltage of the transistor and are usually selected in a range 1.times.10.sup.15 .about.1.times.10.sup.17 cm.sup.-3 and in a range 1.about.10 .mu.m, respectively.
After the formation of the epitaxial layer, a thick oxide film (referred to as "LOCOS oxide film", hereinafter) 5 for separation between semiconductor elements is formed by using usual selective oxidation. Thereafter, N.sup.+ type diffusion layers 6a and 6b which finally form a collector lead diffusion layer for the NPN transistor and a base lead diffusion layer of the L-PNP transistor, respectively, are diffused up to the N.sup.+ type buried layer 2.
Then, a P.sup.+ type insulating diffusion layer 7 for separation between semiconductor elements is diffused up to the P.sup.+ type buried layer 3. Boron is ion-injected to a region which finally forms a base of the NPN transistor with using a photo resist 14 as a mask, resulting in a P type base diffusion layer 8. Conditions of the ion injection of boron depend upon the breakdown voltage and performance of the transistor. It is, however, preferable to select injection energy and dose in a range 10.about.60 KeV and a range 1.about.5.times.10.sup.13 cm.sup.-2, respectively.
Then, as shown in FIG. 4(b), a portion of a thin oxide film on a surface of the base diffusion layer 8 of the NPN transistor is removed and then a polycrystalline silicon layer 9 is deposited thereon to a thickness of 1000.about.3000 .ANG.. After an N type impurity such as arsenide is added to the polycrystalline silicon layer 9 at high density, an N.sup.+ type emitter diffusion layer 10 by heat-treating the wafer in nitrogen atmosphere at 900.about.1000.degree. C. for about 10 minutes. When the addition of arsenide to the polycrystalline silicon layer is to be performed by ion-injection, the injecting conditions are selected such that injection energy and dose of arsenide are in a range of 50.about.90 KeV and 0.5.about.2.times.10.sup.16 cm.sup.-2, respectively.
Then, as shown in FIG. 4(c), the polycrystalline silicon layer 10 is shaped to a desired configuration through photolithography and anisotropic plasma etching such that the polycrystalline silicon layer functions as a mask in a subsequent step for forming a P.sup.- type graft base (external base) by ion-injection of boron or BF.sub.2, as disclosed in Japanese Patent Laid-open sho 59-147458. That is, the polycrystalline silicon layer is etched such that the polycrystalline silicon layer is left on the N.sup.+ type emitter diffusion layer 10 of the NPN transistor, the N.sup.+ type collector lead diffusion layer 6a and the N.sup.+ type base lead diffusion layer 6b of the L-PNP transistor surrounding the N.sup.+ type emitter diffusion layer 10 and the N.sup.- type epitaxial layer 4 which becomes a base region of the L-PNP transistor. Therefore, the ion-injection of boron or BF.sub.2 for the formation of a P.sup.+ type graft base 11a can be done without necessity of selective etching using photo resist. That is, since the etching is performed for a whole surface of the semiconductor wafer, the number of fabrication steps of the semiconductor device can be reduced.
A P.sup.+ type emitter diffusion layer 11b and a collector diffusion layer 11c of the L-PNP transistor are formed simultaneously with the formation of the P.sup.+ type graft base 11a, although it is not disclosed in the Japanese Patent sho 59-147458.
However, the method of forming a P.sup.+ type graft base of an NPN transistor, a P.sup.+ type collector and emitter regions of an L-PNP transistor in one step is well known. Conditions of the graft base injection may be injection energy of about 30 KeV and dose of 3.about.5.times.10.sup.15 cm.sup.-2 when boron is used as ion material and may be injection energy of 50.about.70 KeV and dose of 3.about.5.times.10.sup.15 cm.sup.-2 when BF.sub.2 is used as ion material.
Finally, as shown in FIG. 4(d), a usual inter-layer insulating film such as a BPSG film 12 and an aluminum wiring 13 are formed, resulting in the semiconductor device.
In the prior art mentioned above, however, there is a problem that current amplification factor of the L-PNP transistor (referred to as "h.sub.FE ", hereinafter) is small. This is because the P.sup.+ type collector diffusion layer of the L-PNP transistor is shallow. In order to solve this problem, Japanese Patent Laid-open Hei 1-261865 proposes to increase h.sub.FE by forming the P.sup.+ type collector diffusion layer deeper. However, since the P.sup.+ type graft base of an NPN transistor, the P.sup.+ type collector of the L-PNP transistor are formed in one step as mentioned above, a new problem occurs that, if the P.sup.+ type collector diffusion layer of the L-PNP transistor is formed deeper, the graft base of the NPN transistor is also made deeper and a capacitance C.sub.JC of a base-collector junction is increased correspondingly, lowering a high frequency characteristics thereof.
In order to make the P.sup.31 type graft base region deeper with sacrifice of the high frequency characteristics of the NPN transistor, it is necessary to push boron ions which are injected into the wafer to form the graft base region deeper by heat-treatment at relatively high temperature. Such heat-treatment at high temperature may influence on the emitter diffusion layer of the NPN transistor such that the emitter diffusion layer becomes deep too much. As a result, the base becomes too thin and the breakdown voltage between the collector and the emitter is lowered by punch-through. If, in order to prevent the punch-through from occurring, the P type base diffusion layer is preliminarily formed deep, the thickness of the N.sup.- type epitaxial density region becomes small and the breakdown voltage between the collector and the base is lowered by punch-through. As a result, the breakdown voltage between the collector and the emitter is lowered.
On the contrary, if, in order to prevent the punch-through from occurring by preliminarily making the N.sup.- type epitaxial layer thick, the P.sup.+ type collector diffusion layer of the L-PNP transistor is not become deep relatively and a substrate current of the L-PNP transistor is increased. As a result, h.sub.FE can not be increased as expected.
Further, in the prior art technology, a layout of elements is difficult since the potential of the polycrystalline silicon layer formed on the base region of the L-PNP transistor must be maintained at the highest potential, that is, a source voltage.
If the polycrystalline silicon layer is left floating, a leakage current may flow between the collector and the emitter due to a capacitive coupling therebetween.
Further, the polycrystalline silicon layer becomes a low potential for some reason, an inversion layer may be produced in a surface of the base region, causing the leakage current to flow between the collector and the emitter, too.
Therefore, it is necessary to provide a wiring such that the potential of the polycrystalline silicon layer of the L-PNP transistor becomes maximum, which causes the layout of the elements to be difficult.
Further, in order to provide the wiring on the polycrystalline silicon layer, a portion of the polycrystalline silicon layer which has an annular or closed shape must be extended onto the LOCOS oxide film. In doing so, a portion of the P.sup.+ type collector diffusion layer which also has an annular or closed shape is cut out. Therefore, the P.sup.+ type collector diffusion layer does not completely surround the emitter diffusion layer, causing h.sub.FE to be lowered and the substrate current to be increased.